Bug in VHDL color coding

Andrey Ash

The following code would not always get proper color coding. Usually it would pick an end of any line in the generic description, i.e. after the “&” sign, and after that line no code will be color coded. When one enters any character at that line, the color coding comes back. This bug comes back when scrolling around. Below is the code example.

----------------------------------------------------------------
-- Comment
test_inst : entity work.test_top
    generic map
    (
        co_cfg_filename =>
        -- synthesis translate_off
        "$PRJ_DIR\rtl\test\"&
        -- synthesis translate_on
        "ram_init.mif",
        bp_mem_cfg_filename => 
        -- synthesis translate_off
        "$PRJ_DIR\rtl\test\"&
        -- synthesis translate_on
        "bram_init.mif",
        mi_mem_cfg_filename =>
        -- synthesis translate_off
        "$PRJ_DIR\rtl\test\"&
        -- synthesis translate_on
        "mram_init.mif",
        c_mem_cfg_filename => 
        -- synthesis translate_off
        "$PRJ_DIR\rtl\test\"&
        -- synthesis translate_on
        "cram_init.mif"
    )
    port map
    (
        rst_in => rst,
        clk_in => clk_in,
        test_out_ram_wea => test_out_ram_wea,
        test_out_ram_addra => test_out_ram_addra,
        test_out_ram_dina => test_out_ram_dina,
        ram_douta => ram_douta
    );

Andrey Ash

You can actually see wrong color coding in the example here also, it thinks the last “-- synthesis translate_on” comment continues forever, which is not the case.