Function List for VHDL



  • Hi.

    I want to create a function list of VHDL file contents.
    My problem: how do I define concurrent statements on the same hierarchy level of code?

    An example Code:


    entity X is

    end X;
    ARCHITECTURE y OF X IS
    BEGIN
    instance : comp PORT MAP (…);
    instance2 : comp PORT MAP (…);
    instance3 : comp PORT MAP (…);

    name: PROCESS (…)
    END y;


    I want to find:

    • one entity
    • one architecture
    • all instance statements
    • all process statements

    Do I have to create one super-complex regexpression, or can I use several expressions?



  • Hello @Dirk-Hölscher,

    you can use multiple regex to find the “functions” but you need to define a main regex which includes all
    possible “functions”. See here for more information.

    Cheers
    Claudia



  • Thanks for your reply. I’ve already read the official documentation,

    Let’s say I would use “^.*$” as mainExp, which would find any line…
    If I have understood correctly, I can use multiple <nameExpr> entries, but they will depend on each other:
    The first entry will be called on the found string provided by mainExp, the second entry would be called on the search result provided by first entry, and so on…

    So I hope there’s a way to use the results from mainExp multiple times to find real positives… But I guess this is not possible…

    BTW: My current line is following beast:
    ^[\t ]([\w]+[\t ]:)([\t ][\w]+[\t ])[\t ](COMPONENT|PROCESS|ENTITY|ARCHITECTURE)[\t ][A-Za-z0-9_(), ]*(?!;)$
    Beautiful, and easy to understand, isn’t it? :-)



  • I see the beast but where is the beauty?? ;-D

    So I hope there’s a way to use the results from mainExp multiple times to find real positives… But I guess this is not possible…

    That’s exactly what I understood, each name expr is called against the mainExpr match.
    When one name expr matches the rest will be ignored.

    Your regex starts with [\t ] which means your code must either start with a tab or a space or should it be [\t ]*
    In regards to your example can entity act like a class? Could there be a instance within entity?
    Is it a complete example? Actually I have no idea of VHDL and even don’t konw what it is used for.

    Cheers
    Claudia



  • @Claudia-Frank said:

    Your regex starts with [\t ] which means your code must either start with a tab or a space or should it be [\t ]*
    In regards to your example can entity act like a class? Could there be a instance within entity?
    Is it a complete example? Actually I have no idea of VHDL and even don’t konw what it is used for.

    There are several asterisks missing, seems to have something to do with this community software…

    When looking on notepad’s function list webpage, following is stated:

    The nodes functionName and className have the same structure, and they have the same parsing behaviour. For example, in the functionName node, we got 2 nameExpr nodes:
    If the function parser find the first result by mainExpr attribute, then it will use the first nameExpr to search in the first result, if found (the 2nd result), then it will use the 2nd nameExpr to search in the 2nd result. If found, then the function name is solved.

    So it simply seems to not be possible to use the mainexp multiple times.

    And vhdl is the short form of “very high speed integrated curcuit (VHSIC) hardware description language”.
    It looks like a normal programming language, but instead of execute the code on a processor, this language is used to create real hardware. With vhdl, you can create a CPU (or a CAN controller, network cards, …), not just using it :-)
    The main difference between VHDL and e.g. C is, that C code is executed serially, while VHDL instantiates hardware in parallel, so that you can do many tasks at the same time…



  • @Dirk-Hölscher

    now I see where my confusion comes from.
    The wiki states something different but from testing it looks like you are right.

    <function> parsers

    A <function> has a single attribute, mainExpr, which is a regular expression matching the declaring part of the function, up to the start of its body. The default file adds a displayMode attribute to most <function> and <classsRange> parsers, but it does not appear to be used anywhere as of v6.6.6.

    It contains a single <functionName> container tag, which contains one or more <funcNameExpr/> tag(s). Each of these has a single expr attribute, which is a regular expression. To find the name of a function, each expr attributes is searched in turn in the data mainExpr matched. First non empty result displays as the function name.

    Depending on an example like this

    ------------------------------------------------------------------------
    -- Simple Microprocessor Design (ESD Book Chapter 3)
    -- Copyright Spring 2001 Weijun Zhang
    --
    -- Control Unit composed of Controller, PC, IR and multiplexor
    -- VHDL structural modeling
    -- ctrl_unit.vhd
    ------------------------------------------------------------------------
    
    library	ieee;
    use ieee.std_logic_1164.all;  
    use ieee.std_logic_arith.all;			   
    use ieee.std_logic_unsigned.all;
    
    entity ctrl_unit is
    port(	clock_cu:	in 	std_logic;
        rst_cu:		in 	std_logic;
        PCld_cu:	in 	std_logic;
        mdata_out: 	in 	std_logic_vector(15 downto 0);
        dpdata_out:	in 	std_logic_vector(15 downto 0);
        maddr_in:	out 	std_logic_vector(15 downto 0);		  
        immdata:	out 	std_logic_vector(15 downto 0);
        RFs_cu:		out	std_logic_vector(1 downto 0);
        RFwa_cu:	out	std_logic_vector(3 downto 0);
        RFr1a_cu:	out	std_logic_vector(3 downto 0);
        RFr2a_cu:	out	std_logic_vector(3 downto 0);
        RFwe_cu:	out	std_logic;
        RFr1e_cu:	out	std_logic;
        RFr2e_cu:	out	std_logic;
        jpen_cu:	out 	std_logic;
        ALUs_cu:	out	std_logic_vector(1 downto 0);	
        Mre_cu:		out 	std_logic;
        Mwe_cu:		out 	std_logic;
        oe_cu:		out 	std_logic
    );
    end ctrl_unit;
    
    architecture struct of ctrl_unit is
    
    component controller is
    port(	clock:		in std_logic;
        rst:		in std_logic;
        IR_word:	in std_logic_vector(15 downto 0);
        RFs_ctrl:	out std_logic_vector(1 downto 0);
        RFwa_ctrl:	out std_logic_vector(3 downto 0);
        RFr1a_ctrl:	out std_logic_vector(3 downto 0);
        RFr2a_ctrl:	out std_logic_vector(3 downto 0);
        RFwe_ctrl:	out std_logic;
        RFr1e_ctrl:	out std_logic;
        RFr2e_ctrl:	out std_logic;						 
        ALUs_ctrl:	out std_logic_vector(1 downto 0);	 
        jmpen_ctrl:	out std_logic;
        PCinc_ctrl:	out std_logic;
        PCclr_ctrl:	out std_logic;
        IRld_ctrl:	out std_logic;
        Ms_ctrl:	out std_logic_vector(1 downto 0);
        Mre_ctrl:	out std_logic;
        Mwe_ctrl:	out std_logic;
        oe_ctrl:	out std_logic
    );
    end component;
    
    component IR is
    port(	IRin: 		in std_logic_vector(15 downto 0);
        IRld:		in std_logic;
        dir_addr:	out std_logic_vector(15 downto 0);
        IRout: 		out std_logic_vector(15 downto 0)
    );	
    end component;
    
    component PC is	  
    port(	PCld:	in std_logic;
        PCinc:	in std_logic;
        PCclr:	in std_logic;
        PCin:	in std_logic_vector(15 downto 0);
        PCout:	out std_logic_vector(15 downto 0)
    );
    end component;	 
    
    component bigmux is
    port( 	Ia: 	in std_logic_vector(15 downto 0);
        Ib: 	in std_logic_vector(15 downto 0);
        Ic:	in std_logic_vector(15 downto 0);
        Id:	in std_logic_vector(15 downto 0);
        Option:	in std_logic_vector(1 downto 0);
        Muxout:	out std_logic_vector(15 downto 0)
    );
    end component;
    
    signal IR_sig: std_logic_vector(15 downto 0);
    signal PCinc_sig, PCclr_sig, IRld_sig: std_logic;
    signal Ms_sig: std_logic_vector(1 downto 0);
    signal PC2mux: std_logic_vector(15 downto 0);
    signal IR2mux_a, IR2mux_b: std_logic_vector(15 downto 0);
    
    begin
    
      IR2mux_a <= "00000000" & IR_sig(7 downto 0);
      IR2mux_b <= "000000000000" & IR_sig(11 downto 8);	
      immdata <= IR2mux_a;
      
      U0: controller port map(  clock_cu,rst_cu,IR_sig,RFs_cu,RFwa_cu,
                    RFr1a_cu,RFr2a_cu,RFwe_cu,RFr1e_cu,
                    RFr2e_cu,ALUs_cu,jpen_cu,PCinc_sig,
                    PCclr_sig,IRld_sig,Ms_sig,Mre_cu,Mwe_cu,oe_cu);
      U1: PC port map(PCld_cu, PCinc_sig, PCclr_sig, IR2mux_a, PC2mux);
      U2: IR port map(mdata_out, IRld_sig, IR2mux_a, IR_sig);
      U3: bigmux port map(dpdata_out,IR2mux_a,PC2mux,IR2mux_b,Ms_sig,maddr_in);
    
    BEGIN
    instance : comp PORT MAP (…);
    instance2 : comp PORT MAP (…);
    instance3 : comp PORT MAP (…);
    
    name: PROCESS (…)
    end struct;
    

    I would get a result which is

    entity ctrl_unit
    architecture struct
    component controller
    component IR
    component PC
    component bigmux
    instance : comp
    instance2 : comp
    instance3 : comp
     PROCESS
    

    generated by a function list configuration like

            <parser id="vhdl_syntax" displayName="VHDL" commentExpr="">
                <function mainExpr="[\t ]*(entity|architecture|component|instance[\d]*\h*:|(?<=name:\h)PROCESS)\h[\w]*((?=is)|(?=\h)|(?=\())" displayMode="$functionName$">
                    <functionName>
                        <nameExpr expr=".+"/>
                    </functionName>
                </function>
            </parser>
    

    Cheers
    Claudia



  • Thanks for your help.
    my current version looks like this:

    <parser id="vhdl_syntax" displayName="VHDL" >
        <function 
          mainExpr="^[\t ]*([\w]+[\t ]*:)?([\t ][\w]+[\t ])*[\t ]*(COMPONENT|PROCESS|ENTITY|ARCHITECTURE)[\t ]*[A-Za-z0-9_\(\), ]*(?!\;)$"
          displayMode="$functionName">
            <functionName>
               <nameExpr expr="[\w].*" />
            </functionName>
        </function>
    </parser>
    

    Both versions have theirs flaws and advantages, so I think I will combine them somehow to optimise results…


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