User-Defined Language: cannot make Extras2 work with Suffix1

[ianpo100]

Hello!

I’m trying to set up my own syntax highlighting for VerilogHDL.
Binary and Decimal numbers i has successfully set up ( Suffix1='b 'd ) - they are yellow now as i wanted.
Problem is, i cannot set up Hexadecimals the same way. I added 'h to Suffix1 and a-f A-F to Extras2 but it’s not working: numbers like 8’hF8 are still grey.
I followed advices from https://ivan-radic.github.io/udl-documentation/
What do i do wrong?

        <Keywords name="Numbers, extras2">A B C D E F a b c d e f</Keywords>
        <Keywords name="Numbers, suffix1">&apos;b &apos;d &apos;h</Keywords>

[fuhrmanator]

numbers like 8’hF8 are still grey.

Did you mean 8F8’h ? Otherwise, your suffix 'h is not a suffix.

Also, is it possible you’re mixing apostrophe characters? There are two (making them big so you can see the difference):

’ vs '

Your quoted text number looks like this:

8’hF8

whereas your suffix is defined as

Suffix1='b 'd

The XML shows also you’re defining it as ' or

'

[ianpo100]

Thanks for reply, fuhrmanator!

There’s no mistake - it’s 8’hF8 with &apos ( it appears as ’ in preview already, funnily enough ).
'b and 'd work as suffix OK, even if they have digit(s) after them.
Is there any way to highlight the numbers with 'h inside?

[PeterJones]

The difference is probably because 'b and 'd will have normal digits (0-1 or 0-9) both before and after the 'b or 'd, whereas 'h will also have letters after. And since UDL defines it as a suffix, not an infix, it gets confused once there’s a non-numeric after the suffix. You might try to define all the hex prefixes you generally use in your Verilog in the Prefix 2 entry:

<Keywords name="Numbers, prefix2">1&apos;h 2&apos;h 3&apos;h 4&apos;h 5&apos;h 6&apos;h 7&apos;h 8&apos;h 12&apos;h 16&apos;h 32&apos;h 64&apos;h</Keywords>

However, if you happened to have an 11-bit segment you tried to access as 11’h75A, but hadn’t included 11'h in your prefix 2, it wouldn’t highlight for you.

Is there a reason you aren’t using the built-in Verilog lexer? It defaults to Verilog for extensions v, sv, vh, and svh; I added vams (using Settings > Style Configurator > Verilog > User Ext).

I’m not a huge user of Verilog and its variants, but in the times I have been editing such files, I haven’t noticed any significant deficiency. It properly highlights any bitness for hex, binary, and decimal that I’ve noticed, and the other syntax I’ve used has looked reasonable.

If there are words that aren’t getting marked up using the Verilog lexer, you can use the Style Configurator to add custom words: both INSTRUCTION WORD and KEYWORD have a User-defined box for extending what gets highlighted.