The difference is probably because 'b and 'd will have normal digits (0-1 or 0-9) both before and after the 'b or 'd, whereas 'h will also have letters after. And since UDL defines it as a suffix, not an infix, it gets confused once there’s a non-numeric after the suffix. You might try to define all the hex prefixes you generally use in your Verilog in the Prefix 2 entry:
<Keywords name="Numbers, prefix2">1'h 2'h 3'h 4'h 5'h 6'h 7'h 8'h 12'h 16'h 32'h 64'h</Keywords>
However, if you happened to have an 11-bit segment you tried to access as 11’h75A, but hadn’t included 11'h in your prefix 2, it wouldn’t highlight for you.
Is there a reason you aren’t using the built-in Verilog lexer? It defaults to Verilog for extensions v, sv, vh, and svh; I added vams (using Settings > Style Configurator > Verilog > User Ext).
I’m not a huge user of Verilog and its variants, but in the times I have been editing such files, I haven’t noticed any significant deficiency. It properly highlights any bitness for hex, binary, and decimal that I’ve noticed, and the other syntax I’ve used has looked reasonable.
If there are words that aren’t getting marked up using the Verilog lexer, you can use the Style Configurator to add custom words: both INSTRUCTION WORD and KEYWORD have a User-defined box for extending what gets highlighted.
